Purwarupa Perangkat Keras untuk Eksekusi Algoritma AES Berbasis FPGA


Nia Gella Augoestien(1*), Agfianto Eko Putra(2)

(1) Department of Computer Science and Electronics, Universitas Gadjah Mada
(2) Department of Computer Science and Electronics, Universitas Gadjah Mada
(*) Corresponding Author


 AES cryptography algorithm is a tool which often using to protect confidentiality of data.Confidentiality of data is principle parameter of data security in various system. Data security achieve by collaborated AES algorithm with another cryptosystem tools. Therefore, limited resource hardware to excecuteAES algorithm is very important.

            This research proposed hardware prototype for excecuting AES algorithm based on FPGA. Optimumresource utilizing become basic priority in this design. So that, we are using resource sharing between hardware for encryption and decryption, iteratif architecture on round level, pipeline architecture on transformation level with 32-bit architecture at design to attain optimum resource utilizing.

            Hardware prototype in this research use FPGA Xilinx Spartan®-6 (XC6LX16-CS324), encryption and decryption have been done in this hardware prototype. This prototype have 1,94Mbps/Slice hardware efficiency, 308,96Mbps throughput with only using 6% resource that available on this FPGA.


AES Algorithm, FPGA, resource sharing, iterative, pipeline

Full Text:



[1]Martin, K., 2012, Everyday Cryptography Fundamental Principles and Applications, Oxford University Press, London.

[2]Jamal, H. dan Hussain, U., 2012, An Efficient High Throughput FPGA Implementation of AES for Multi-Gigabit Protocols, International Conference on Frontiers of Information Technology, 12, pp. 215-218.

[3]Henriquez, F. R., Saqib, N. A., Perez, A. D. dan Koc, C. K., 2006, Cryptographic Algorithms on Reconfigurable Hardware, Springer, New York.

[4]Deshpande, A. M, Deshpande, M. S, dan Kayatanavar, D. N., 2009, FPGA Implementation of AES Encryption and Decryption, International Conference on “Control, Automation Communication and Energy Conservation”, 6, pp 1-6.

[5]Ghaznazi, S., Gebotys, C., dan Elbaz., R., 2009, Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation, International Conference on Reconfigurable Computing and FPGAs, 52, pp. 219-224.

[6] Benaissa, M., dan Chu, J., 2012, Low area memory-free FPGA implementation of AES algorithm, pp. 623-626.

[7] Benhadjyoussef, N., Machhout, M., Elhadjyoussef, W., dan Tourki, R., 2012, A compact 32-Bit AES design for embedded system, International Conference on Design & Technology of Integrated Systems in Nanoscale Era, pp 1-4

[8] Kshirsagar, R. V., dan Vyawahare, M. V., 2012, FPGA Implementation of High speed VLSI Architectures for AES Algorithm, International Conference on Emerging Trends in Engineering and Technology, 5, pp. 239-242.

[9]Krukowski, L dan Sugier, J., 2008, Organization of AES Cryptographic Unit for Low Cost FPGA Implementation, Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX 2008, 36,pp 347-354.

[10]Matsuoka, S. dan Ichikawa, S., 2012, Reduction of power consumption in key-specific AES circuits, Third International Conference on Networking and Computing, 3, pp. 323-325.

DOI: https://doi.org/10.22146/ijeis.7644

Article Metrics

Abstract views : 2502 | views : 2483


  • There are currently no refbacks.

Copyright (c) 2015 IJEIS - Indonesian Journal of Electronics and Instrumentation Systems

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Copyright of :
IJEIS (Indonesian Journal of Electronics and Instrumentations Systems)
ISSN 2088-3714 (print); ISSN 2460-7681 (online)
is a scientific journal the results of Electronics
and Instrumentations Systems
A publication of IndoCEISS.
Gedung S1 Ruang 416 FMIPA UGM, Sekip Utara, Yogyakarta 55281
Fax: +62274 555133
email:ijeis.mipa@ugm.ac.id | http://jurnal.ugm.ac.id/ijeis

View My Stats1
View My Stats2